An Optimal Gate Design for the Synthesis of Ternary Logic Circuits

Department of Electrical EngineeringOver the last few decades, CMOS-based digital circuits have been steadily developed. However, because of the power density limits, device scaling may soon come to an end, and new approaches for circuit designs are required. Multi-valued logic (MVL) is one of the new approaches, which increases the radix for computation to lower the complexity of the circuit. For the MVL implementation, ternary logic circuit designs have been proposed previously, though they could not show advantages over binary logic, because of unoptimized synthesis techniques. In this thesis, we propose a methodology to design ternary gates by modeling pull-up and pull-down operations of the gates. Our proposed methodology makes it possible to synthesize ternary gates with a minimum number of transistors. From HSPICE simulation results, our ternary designs show significant power-delay product reductions; 49 % in the ternary full adder and 62 % in the ternary multiplier compared to the existing methodology. We have also compared the number of transistors in CMOS-based binary logic circuits and ternary device-based logic circuits We propose a methodology for using ternary values effectively in sequential logic. Proposed ternary D flip-flop is designed to normally operate in four-edges of a ternary clock signal. A quad-edge-triggered ternary D flip-flop (QETDFF) is designed with static gates using CNTFET. From HSPICE simulation results, we have confirmed that power-delay-product (PDP) of QETDFF is reduced by 82.31 % compared to state of the art ternary D flip-flop. We synthesize a ternary serial adder using QETDFF. PDP of the proposed ternary serial adder is reduced by 98.23 % compared to state of the art design.ope

Self-selective ferroelectric memory realized with semimetalic graphene channel

A new concept of read-out method for ferroelectric random-access memory (FeRAM) using a graphene layer as the channel material of bottom-gated field effect transistor structure is demonstrated experimentally. The transconductance of the graphene channel is found to change its sign depending on the direction of spontaneous polarization (SP) in the underlying ferroelectric layer. This indicates that the memory state of FeRAM, specified by the SP direction of the ferroelectric layer, can be sensed unambiguously with transconductance measurements. With the proposed read-out method, it is possible to construct an array of ferroelectric memory cells in the form of a cross-point structure where the transconductance of a crossing cell can be measured selectively without any additional selector. This type of FeRAM can be a plausible solution for fabricating high speed, ultra-low power, long lifetime, and high density 3D stackable non-volatile memory

Ternary full adder using multi-threshold voltage graphene barristors

Ternary logic circuit has been studied for several decades because it can provide simpler circuits and subsequently lower power consumption via succinct interconnects. We demonstrated a ternary full adder exhibiting a low power-delay-product of ~10-16 J, which is comparable with the binary equivalent circuit. The ternary full adder was modeled using device parameters extracted from the experimentally demonstrated multi-Vth ternary graphene barristors

Low-Power Integrated-Circuit Implementation Exploiting System and Application Information /

A primary design goal for VLSI systems is to achieve low energy consumption while maintaining high performance. Increasing thermal densities and the portability of emerging computing systems demand further reduction of design power. However, in integrated-circuit (IC) designs, there is a tradeoff between energy and performance, and the solution space for any given design is bounded by the lowest possible energy and the highest possible performance. To minimize energy consumption under performance constraints, we seek to optimize the design up to the Pareto frontier of energy versus performance. Many system- and design-level techniques have been introduced to extend the achievable energy-performance envelope. For low-power IC implementation, this thesis first explores traditional design methodologies, which include gate sizing optimization and power gating. Gate sizing is an effective approach to optimize the tradeoff of power and delay in VLSI design. A sensitivity-guided metaheuristics approach is presented for high-quality, large-scale gate sizing. The proposed gate sizing method can minimize the power (energy) consumption under the timing (performance) constraint. Power gating is one of the most effective solutions available to reduce leakage power. However, power gating has not been practically usable in an active mode. In this thesis, a data-retained power gating is presented to enable power gating of flip-flops during the active mode. Extensions of the energy-performance envelope can be achieved with new system- and design-level techniques such as (i) error-tolerant design, (ii) dynamic voltage and frequency scaling (DVFS), (iii) approximate arithmetic design, and (iv) adaptive power gating. However, with the new system-level techniques for energy-efficient design, conventional CAD flows or designs may constrain or reduce the benefits realized from these techniques; hence, new design methodologies are necessary for each technique. The innovative techniques proposed in this thesis exploit the system and application information, and connect them into design optimization and physical implementation to enable more energy-efficient designs. In other words, if we have better communication between system design and chip implementation, we can improve the design quality in terms of the low energy consumption. First, error-tolerant design allows timing errors, so frequently exercised paths should be optimized to reduce the error rate of the design. This means that a function-aware design optimization is required for the error-tolerant design. Second, to minimize lifetime energy in DVFS design, operating scenarios should be considered and scenario- aware optimization is required. Third, for the approximate designs, a tradeoff between data accuracy and power reduction can be used. Finally, to make an adaptivepower gating, we should retain internal data and control wake-up overheads. In each of these four directions, this thesis proposes novel optimization and design flows which expand the achievable envelope of low-power, high-performance VLSI system desig

A Novel Approximate Synthesis Flow for the Energy-Efficient FIR filter

The portability of emerging computing systems demands further reduction in the power consumption of their components. Ap- proximate computing can reduce power consumption by using a simplified or an inaccurate circuit. In this paper, the energy efficiency of a finite impulse response (FIR) filter is improved through approximate computing. We propose an approximate synthesis technique for an energy-efficient FIR filter with an ac- ceptable level of accuracy. We employ the common subexpression elimination (CSE) algorithm to implement the FIR filter and re- place conventional adder/subtractors with approximate ones. While yielding acceptable rates of accuracy, the proposed flow can attain a maximum energy saving of 50.7% in comparison with conventional FIR filter designs.2

Comparative Analysis between Verilog and Chisel in RISC-V Core Design and Verification

Chisel is a hardware design method that uses Scala programming language, and exploits many useful features of Scala like object-oriented programming and functional programming. By comparing two equivalent RISC-V core designs, one implemented using each hand-written Verilog code and one using Chisel, this paper compares manual Verilog coding and Chisel coding. The comparison metrics are source-code density, area of synthesized hardware, and RTL simulation run-Time. As a result, Chisel is proved to be more productive than Verilog.1

Fast Chip-Package-PCB Coanalysis Methodology for Power Integrity of Multi-domain High-Speed Memory: A Case Study

The power integrity of high-speed interfaces is an increasingly important issue in mobile memory systems. However, because of complicated design variations such as adjacent VDD domain coupling, conventional case-specific modeling is limited in analyzing trends in results from parametric variations. Moreover, conventional industrial methods can be simulated only after the design layout is completed and it requires a lot of back-annotation processes, which result in delayed delays time to market. In this paper, we propose a chip-package-PCB coanalysis methodology applied to our multi-domain high-speed memory system model with a current generation method. Our proposed parametric simulation model can analyze the tendency of power integrity results from variable sweeps and Monte Carlo simulations, and it shows a significantly reduced runtime compared to the conventional EDA methodology under JEDEC LPPDR4 environment.1

CPR: Crossbar-grain Pruning for an RRAM-based Accelerator with Coordinate-based Weight Mapping

Resistive random access memory (RRAM)-based crossbar arrays with the process-in-memory (PIM) approach are emerging as a promising technique for accelerating deep neural networks (DNNs) with their high-speed and multi-level programming characteristics. The computation performance of crossbars can be improved by pruning techniques, however, tightly coupled bitlines and wordlines in PIM architectures make the exploitation of data sparsity rather difficult. Therefore, the hardware dependency has to be carefully considered for the application of pruning techniques. In this work, we develop an RRAM-based DNN accelerator, CPR, with (i) a coordinate-based weight mapping method and (ii) a crossbar-grain pruning algorithm. This mapping method locates weights to different crossbar arrays according to their spatial location, thereby increasing input data reuse and reducing waste of energy and latency. We minimize the unused space in crossbars to increase the area efficiency by combining multiple crossbar subarrays. Moreover, by retaining only the desired number of crossbar subarrays in the processing-element (PE) and pruning the rest, we preserve the high computing parallelism without violating the hardware dependency. The overhead of additional circuits is not significant compared to the overall chip design. The experimental results show that our weight mapping method outperforms the conventional method by 1.6 × in TOPs/W with a smaller area. The proposed pruning algorithm reduces the latency by 71%, energy by 70%, and area by 84% from baseline implementation.1

Data Protection Method for Flash Memory in Serial Peripheral Interface

We propose a general flash protection function for flash read/write/erase operations, to provide security for the contents. The 'read protection' changes all outputs of flash memory to specific data and the 'write/erase protection' ensures that all commands to flash memory are ignored. We also provide a function that can disable or restore the flash protection whenever a user wants by providing a valid password. The flash protection can be used in any kind of flash memory because it works at the Serial Peripheral Interface (SPI) level.1

Novel approximate synthesis flow for energy-efficient FIR filter

The portability of emerging computing systems demands further reduction in the power consumption of their components. Approximate computing can reduce power consumption by using a simplified or an inaccurate circuit. In this paper, the energy efficiency of a finite impulse response (FIR) filter is improved through approximate computing. We propose an approximate synthesis technique for an energy-efficient FIR filter with an acceptable level of accuracy. We employ the common subexpression elimination (CSE) algorithm to implement the FIR filter and replace conventional adder/subtractors with approximate ones. While yielding acceptable rates of accuracy, the proposed flow can attain a maximum energy saving of 50.7% in comparison with conventional FIR filter designs